1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly, to the precharge function of a semiconductor memory device which sets the potential of bit lines connected to memory cells to a given level when data is read from the memory cells.
2. Description of the Related Art
The electrical characteristics of memory cells, data lines, and select lines are key aspects when designing large arrays of high speed memory cells. Data line delay characteristics, for example, are a particular concern because they traverse the entire memory array and produce large capacitive loads. Unfortunately, during memory cell read operations, the memory cells themselves must drive the data line capacitance. Consequently, one challenge in designing memory cells is to drive a data line high when a memory cell pull up device charges the capacitance of the data line, and to do so without an unacceptable pull up delay.
One way to minimize the pull up time for highly capacitive lines, is to pull the line to a voltage above the threshold logic when it is not in use. This technique is called precharge because the line is precharged to a value at or near the high logic potential. When performing data read operations, should precharge operations not be performed, data from the memory cells can be erroneously written and destroyed.
Unfortunately, the amount of power required by the precharge operations is usually greater than that required for other memory cell operations. Consequently, when considering ways to reduce the level of power consumed during memory cell operations, reducing the power consumed during precharge operations is an obvious consideration. Moreover, reducing the amount of power consumed during memory cell operations presents the possibility that data access can be performed at higher speeds.
FIG. 1 illustrates a conventional static random access memory (SRAM) 40. The SRAM 40 comprises a memory cell array 41, a precharger 42, a row decoder 43, a column switch 44, a column decoder 45, an address buffer 46, a sense amplifier 47, a write amplifier 48, a control buffer 49 and a clock generator 51.
FIG. 2 shows memory cell array 41, precharger 42, and column switch 44 in detail. The cell array 41 is provided with a plurality of word lines WL1 to WLm, a plurality of bit line pairs (BL1, /BL1) to (BLn, /BLn). A memory cell C.sub.0 is connected by a pair of bit lines and a pair of word lines. Each of the cells C.sub.0 is formed by a first and a second invertor 52, and 53, and a first and a second gate transistor 54 and 55. When one of the word lines is selected from among each of the word lines WL1 to WLm, and when the potential of the selected word line rises high, data is output from the cell array 41. The data is output from a plurality of cells C.sub.0 connected with the selected word line to the associated bit line pairs (BL1,/BL1) to (BLn,/BLn), respectively.
The precharger 42 comprises a plurality of circuits 42A.sub.1 to 42A.sub.n formed by the 4th to 6th transistors 56 to 58. Each of the circuits 42A.sub.1 to 42A.sub.n precharges the associated bit line pairs (BL1, /BL1) to (BLn, /BLn) by means of a power-supply V.sub.DD. Specifically, the 4th to 6th transistors 56 to 58 turn on to precharge the bit line pairs during the period in which the potential of the clock signal CLK, output by the clock generator 51 during timing cycle t0 (see FIG. 3), is high.
As shown in FIG. 1, the address buffer 46 holds an address signal AD from a CPU or other type of controller (not shown), in synchronism with the rising of the clock signal CLK, and then separates the address signal AD into a row address signal ADR and a column address signal ADC. The address buffer 46 next supplies the row address signal ADR to the row decoder 43, and the column address signal ADC to the column decoder 45.
The control buffer 49 receives the read enable signal RE and the write enable signal WE from the controller, and outputs control signals to decoders 43 and 45 in accordance with both signals RE and WE. The buffer 49 further outputs the read enable signal RE to the sense amplifier 47, and the write enable signal WE to the write amplifier 48.
The row decoder 43 decodes the address signal ADR in response to the control signal input from the control buffer 49, and generates a selection signal SRD. The selection signal SRD is an instruction related to the selection of one of the word lines WL1 to WLm. The row decoder 43 then outputs the selection signal SRD to the memory cell array 41.
The column decoder 45 decodes the address signal ADC in response to the control signal input from the control buffer 49, and generates a selection signal SCD, thus outputting the selection signal SCD to the column switch 44 connected to the cell array 41.
As shown in FIG. 2, the column switch 44 is provided with a plurality of switching pairs (SC.sub.1, SD.sub.1) to (SC.sub.n, SD.sub.n), and is connected to the sense amplifier 47 and the write amplifier 48 through the output line pair (LC.sub.0, /LC.sub.0). Based on the input selection signal SCD, one of the switching pairs (SC.sub.1, SD.sub.1) to (SC.sub.n, SD.sub.n) is turned on. The column switch 44 selectively connects the output line pair (LC.sub.0,/LC.sub.0) and the bit line pair corresponding to the actuated switching pair.
The sense amplifier 47 is activated in response to the input read enable signal RE, and amplifies the data on the cell C.sub.0. This data is read out on the selected bit line pair and the output line pair (LC.sub.0, /LC.sub.0) when the clock signal CLK pulse is input high. Then, the sense amplifier 47 outputs the amplified data, i.e., read data RD.sub.0, onto the data bus (not shown) which is connected to the SRAM.
The write amplifier 48 connected to the data bus (not shown) is activated in response to the input write enable signal WE, and writes the data, i.e., write data WD.sub.0, onto the cell C.sub.0 through the output line pair (LC.sub.0,/LC.sub.0), and the selected bit line pair.
When the data is read out from the above-mentioned SRAM 40, the address buffer 46 latches the address signal AD in synchronism with the rising of the clock signal CLK as shown in FIG. 3. Then, the address buffer 46 supplies the row address signal ADR to the row decoder 43, and the column address signal ADC to the column decoder 45.
The row decoder 43 decodes the address signal ADR to the selection signal SRD. Then, based on the signal SRD, a word line WL1 for example is selected. The column decoder 45 decodes the address signal ADC to the selection signal SCD. Then, based on the signal SCD, a pair of switches (e.g., SC.sub.1, SD.sub.1) are turned on, causing the bit line pair (BL1,/BL1) to connect to the output line pair (LC.sub.0, /LC.sub.0). This describes the selection of the cell C.sub.0, connected to the word line WL1 and the bit line pair (BL1, /BL1).
At this time, all of the 4th to 6th transistors 56 to 58 of the precharger 42 are turned on, respectively, during the period when the clock signal CLK is high. Next, the precharger 42 precharges the bit line pairs (BL1, /BL1) to (BLn,/BLn) by means of the power-supply V.sub.DD.
Thus, based on the data on the selected cell C.sub.0, one of the levels of the bit line (BL1, /BL1) is pulled low while the other level is held at the level of the power-supply V.sub.DD. Data can, in this way, be read out onto the bit line pair (BL1, /BL1). The data thus read out is transferred to the sense amplifier 47 through the output line pair (LC.sub.0, /LC.sub.0), In this amplifier 47, the read-out data RD.sub.0 is output after being amplified.
Next, in response to an incremented address signal AD, the address buffer 46 latches the new address signal AD in synchronism with the rising of the clock signal CLK. Here, the row address signal ADR will not change, and the word line WL1 will still remain selected. On the other hand, the column address signal ADC changes, and the bit line pair (BL2,/BL2) (not shown) are connected to the output line pair (LC.sub.0,/LC.sub.0). Hence, the cell C.sub.0 connected to the word line WL1 and the bit line pair (BL2, /BL2) is selected.
At this time, the precharger 42 precharges all the bit line pairs (BL1,/BL1) to (BLn,/BLn) by means of the power-supply V.sub.DD during the period in which the clock signal CLK is high. Data in the selected cell C.sub.0 is then read out onto the bit line pair (BL2, /BL2), and output line pair (LC.sub.0,/LC.sub.0), and output to the sense amplifier 47. The sense amplifier 47 amplifies the read-out data, and outputs it as read-out data RD.sub.0.
Thereafter, the word line is selected in response to the incremented address, and at the same time, the bit line pair is connected to the output line pair (LC.sub.0, /LC.sub.0). In synchronism with the clock signal CLK, the precharger 42 precharges the bit line pairs (BL1, /BL1) to (BLn, /BLn) by means of the power-supply V.sub.DD. Hence, the data on the cell C.sub.0, connected to the selected word line and bit line pair is read out. The sense amplifier 47 amplifies and outputs this data as read-out data RD.sub.0. In this way, as shown in FIG. 3, the sense amplifier 47 outputs the read-out data RD.sub.0 in synchronism with the falling of the clock signal CLK.
However, in the above-mentioned SRAM 40, the precharger 42 must operate in synchronism with the clock signal CLK each time data is read from a specific cell C.sub.0. As a result, precharging is performed with respect to all the bit line pairs (BL1,/BL1) to (BLn,/BLn). This occurs even when the data on a plurality of cells C.sub.0 connected to the same word line should be read out one after another. The precharger 42 in this instance, precharges all the bit line pairs (BL1,/BL1) to (BLn,/BLn). Therefore, this precharger 42 inevitably consumes a great amount of power. This causes the power consumption of the SRAM 40 to increase beyond what is necessary for its intended function.
Also, the sense amplifier 47 outputs the read-out data RD.sub.0 in synchronism with the falling of the clock signal CLK after the precharging is executed. Therefore, when the data on a plurality of cells connected to the same word line is read out one by one. Read out timing of the data in later cells must inevitably be delayed by an amount equivalent to the precharging period.